MAX® 10 FPGA Device Overview

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ID 683658
Date 3/10/2025
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Overview
MAX® 10 FPGA Device Overview x
Key Advantages of MAX® 10 Devices Summary of MAX® 10 Device Features MAX® 10 Device Ordering Information MAX® 10 Device Maximum Resources MAX® 10 Devices I/O Resources Per Package MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Revision History for the MAX® 10 FPGA Device Overview
MAX® 10 Device Ordering Information x
MAX® 10 Device Feature Options
MAX® 10 Vertical Migration Support x
MAX® 10 I/O Vertical Migration Support MAX® 10 ADC Vertical Migration Support
FPGA General Purpose I/O x
MultiVolt I/O Interface LVDS Tunneling Protocol and Interface
Configuration x
Remote System Update Hitless Update
MAX® 10 FPGA Device Overview

Remote System Update

The MAX® 10 devices support remote system updates where you can deploy a new image to a MAX® 10 FPGA in the field over a network.

The remote update process stores the new image on the flash memory, protects the system during reconfiguration, and reconfigures the FPGA to load the new image:

  • Allows flash image update through the On-Chip Flash IP during user mode
  • Stores two images on the flash memory:
    • CFM0—the factory golden image
    • CFM1 and CFM2—the application image
  • Falls back to the factory golden image if the reconfiguration fails
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