MAX® 10 FPGA Device Overview

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ID 683658
Date 3/10/2025
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Overview
MAX® 10 FPGA Device Overview x
Key Advantages of MAX® 10 Devices Summary of MAX® 10 Device Features MAX® 10 Device Ordering Information MAX® 10 Device Maximum Resources MAX® 10 Devices I/O Resources Per Package MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Revision History for the MAX® 10 FPGA Device Overview
MAX® 10 Device Ordering Information x
MAX® 10 Device Feature Options
MAX® 10 Vertical Migration Support x
MAX® 10 I/O Vertical Migration Support MAX® 10 ADC Vertical Migration Support
FPGA General Purpose I/O x
MultiVolt I/O Interface LVDS Tunneling Protocol and Interface
Configuration x
Remote System Update Hitless Update
MAX® 10 FPGA Device Overview

MAX® 10 Device Maximum Resources

Table 4.   Maximum Resource Counts for MAX® 10 Devices
Resource Device
10M02 10M04 10M08 10M16 10M25 10M40 10M50
Logic Elements (LE) (K) 2 4 8 16 25 40 50
M9K Memory (Kb) 108 189 378 549 675 1,260 1,638
User Flash Memory (Kb) 2 96 1,248 1,376 2,368 3,200 5,888 5,888
18 × 18 Multiplier 16 20 24 45 55 125 144
PLL 2 2 2 4 4 4 4
GPIO 246 246 250 320 360 500 500
LVDS Dedicated Transmitter 15 15 15 22 24 30 30
Emulated Transmitter 114 114 116 151 171 241 241
Dedicated Receiver 114 114 116 151 171 241 241
Internal Configuration Image 1 2 2 2 2 2 2
ADC — 1 1 1 2 2 2
2 The maximum possible value including user flash memory and configuration flash memory. For more information, refer to MAX® 10 User Flash Memory User Guide.
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