Key Advantages of MAX® 10 Devices
Summary of MAX® 10 Device Features
MAX® 10 Device Ordering Information
MAX® 10 Device Maximum Resources
MAX® 10 Devices I/O Resources Per Package
MAX® 10 Vertical Migration Support
Logic Elements and Logic Array Blocks
Analog-to-Digital Converter
User Flash Memory
Embedded Multipliers and Digital Signal Processing Support
Embedded Memory Blocks
Clocking and PLL
FPGA General Purpose I/O
External Memory Interface
Configuration
Power Management
Revision History for the MAX® 10 FPGA Device Overview
Clocking and PLL
MAX® 10 devices offer the following resources: global clock (GCLK) networks and phase-locked loops (PLLs) with a 116-MHz built-in oscillator.
MAX® 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to 450 MHz. The GCLK networks have high drive strength and low skew.
The PLLs provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking. The high precision and low jitter PLLs offers the following features:
- Reduction in the number of oscillators required on the board
- Reduction in the device clock pins through multiple clock frequency synthesis from a single reference clock source
- Frequency synthesis
- On-chip clock de-skew
- Jitter attenuation
- Dynamic phase-shift
- Zero delay buffer
- Counter reconfiguration
- Bandwidth reconfiguration
- Programmable output duty cycle
- PLL cascading
- Reference clock switchover
- Driving of the ADC block