MAX® 10 FPGA Device Overview

ID 683658
Date 6/14/2022

Clocking and PLL

Intel® MAX® 10 devices offer the following resources: global clock (GCLK) networks and phase-locked loops (PLLs) with a 116-MHz built-in oscillator.

Intel® MAX® 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to 450 MHz. The GCLK networks have high drive strength and low skew.

The PLLs provide robust clock management and synthesis for device clock management, external system clock management, and I/O interface clocking. The high precision and low jitter PLLs offers the following features:
  • Reduction in the number of oscillators required on the board
  • Reduction in the device clock pins through multiple clock frequency synthesis from a single reference clock source
  • Frequency synthesis
  • On-chip clock de-skew
  • Jitter attenuation
  • Dynamic phase-shift
  • Zero delay buffer
  • Counter reconfiguration
  • Bandwidth reconfiguration
  • Programmable output duty cycle
  • PLL cascading
  • Reference clock switchover
  • Driving of the ADC block