MAX® 10 FPGA Device Overview

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ID 683658
Date 3/10/2025
Public
Document Table of Contents
Document Table of Contents x
MAX® 10 FPGA Device Overview
MAX® 10 FPGA Device Overview x
Key Advantages of MAX® 10 Devices Summary of MAX® 10 Device Features MAX® 10 Device Ordering Information MAX® 10 Device Maximum Resources MAX® 10 Devices I/O Resources Per Package MAX® 10 Vertical Migration Support Logic Elements and Logic Array Blocks Analog-to-Digital Converter User Flash Memory Embedded Multipliers and Digital Signal Processing Support Embedded Memory Blocks Clocking and PLL FPGA General Purpose I/O External Memory Interface Configuration Power Management Revision History for the MAX® 10 FPGA Device Overview
MAX® 10 Device Ordering Information x
MAX® 10 Device Feature Options
MAX® 10 Vertical Migration Support x
MAX® 10 I/O Vertical Migration Support MAX® 10 ADC Vertical Migration Support
FPGA General Purpose I/O x
MultiVolt I/O Interface LVDS Tunneling Protocol and Interface
Configuration x
Remote System Update Hitless Update
MAX® 10 FPGA Device Overview

MAX® 10 I/O Vertical Migration Support

Figure 2. Migration Capability Across MAX® 10 Devices
  • The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Non-migratable devices are omitted. Some packages have several migration paths. Devices with lesser I/O resources in the same path have lighter shades.
  • To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to match the product line with the lowest I/O count.


Note: Before starting migration work, Intel recommends that you verify the pin migration compatibility through the Pin Migration View window in the Quartus® Prime software Pin Planner. For example, not all MAX® 10 devices support 1.0 V I/O.
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