MAX® 10 FPGA Device Overview

ID 683658
Date 6/14/2022


Table 12.  Configuration Features
Feature Description
Dual configuration
  • Stores two configuration images in the configuration flash memory (CFM)
  • Selects the first configuration image to load using the CONFIG_SEL pin
Design security
  • Supports 128-bit key with non-volatile key programming
  • Limits access of the JTAG instruction during power-up in the JTAG secure mode
  • Unique device ID for each Intel® MAX® 10 device
SEU Mitigation
  • Auto-detects cyclic redundancy check (CRC) errors during configuration
  • Provides optional CRC error detection and identification in user mode
Dual-purpose configuration pin
  • Functions as configuration pins prior to user mode
  • Provides options to be used as configuration pin or user I/O pin in user mode
Configuration data compression
  • Decompresses the compressed configuration bitstream data in real-time during configuration
  • Reduces the size of configuration image stored in the CFM
Instant-on Provides the fastest power-up mode for Intel® MAX® 10 devices.
Table 13.  Configuration Schemes for Intel® MAX® 10 Devices
Configuration Scheme Compression Encryption Dual Image Configuration Data Width
Internal Configuration Yes Yes Yes