Intel® Agilex™ Hard Processor System Component Reference Manual

ID 683581
Date 2/07/2023

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Document Table of Contents HPS Peripheral Clocks – Desired Frequencies

The clock frequencies you provide in this section are reported in a Synopsys* Design Constraints File (.sdc) generated by Platform Designer. The .sdc file is referenced in the system .qip file when the system is generated. The grayed out boxes show the frequencies of the various clocks and can only be changed by changing the L3 source clock frequency or by changing the respective clock divider.
Note: GUI interface for this feature will change for Intel® Quartus® Prime Pro Edition version 19.3.