Intel® Agilex™ Hard Processor System Component Reference Manual

ID 683581
Date 2/07/2023

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2.7. Generating and Compiling the HPS Component

The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer project. Perform the following steps:

  1. Generate the design with Platform Designer. The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
    Additionally, while using the FPGA to HPS slave interface in AXI* -4 mode, selecting Load IP-XACT Register Details includes relevant CSR offsets information with an "isPresent" tag in the generated .ip file.
    Figure 29.  Platform Designer Displaying Load IP-XACT Register Details in AXI* -4 Mode
  2. Add <qsys_system_name>.qip to the Intel® Quartus® Prime project. <qsys_system_name>.qip is the Intel® Quartus® Prime IP File for the HPS component, generated by Platform Designer.
    Note: Platform Designer generates pin assignments in the .qip file.
    Figure 30.  Platform Designer Displaying the Pin Assignments
  3. Perform analysis and synthesis with the Intel® Quartus® Prime software.
  4. Compile the design with the Intel® Quartus® Prime software.
  5. Optionally back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.