Intel® Agilex™ Hard Processor System Component Reference Manual

ID 683581
Date 2/07/2023

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3.3. FPGA-to-HPS AXI* Slave Interface

The FPGA‑to‑HPS AXI* slave interface, f2h_axi_slave, is connected to a Mentor Graphics® AXI* slave BFM for simulation with an instance name of f2h_axi_slave_inst. Platform Designer configures the BFM as shown in the following table. The BFM clock input is connected to f2h_axi_clock clock.

Table 22.  Configuration of FPGA-to-HPS AXI* Slave BFM



AXI* Address Width

20 - 37

AXI* Read Data Width


AXI* Write Data Width


AXI* ID Width


You control and monitor the AXI* slave BFM by using the BFM API.