AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.1.1. Limit Reset Usage

Limit resets to design conditions that actually require reset. Limiting resets has the following benefits, especially for a large data path that can cause excessive resource usage:

  • Reduced logic utilization
  • Lower routing congestion
  • Lower data path routing delays
  • Better timing performance
However, you must assert a reset for any register that requires power-up to a known state. The following are some of the design scenarios that require resets:
  • If a watchdog timer detects a fault, then it can generate a reset to the whole system.
  • Status registers that require reset at certain events after taking action to clear any pending errors.
  • Simple counters or state machines that require return to initial states when conditions arise during a normal application run.
  • A flip-flop within a feedback loop requires a reset to bring the register back to a reset state during a normal process.

The following are some of the blocks or registers that can function without resets:

  • Shift registers and data buses accompanied by control signals to signify validity of current values.
  • Designs that use pipeline or delay chains may only require reset at the beginning of the pipeline stage, but not at the succeeding stages. Hold the reset asserted for a duration long enough to flush the entire pipeline.