AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.2.1. Asynchronous Reset Design Strategies

The primary disadvantage of using an asynchronous reset is that the reset is asynchronous both at the assertion and de-assertion of the signal.

The signal assertion is not the problem on the actual connected flip-flop. Even if the flip-flop moves to a metastable state, the flip-flop remains unstable only for a short period of time after assertion. After reset asserts long enough, all registers eventually settle to a reset state.

The problem of the asynchronous reset involves the signal de-assertion. If an asynchronous reset releases at or near the active clock edge, the output of the flip-flop could go to a metastable state, violating the reset recovery time of the flip-flop. The flip-flop then goes to an unknown state that can cause unexpected results upon entering normal operation.

You can insert a synchronously de-asserted reset circuit to prevent this condition. Synchronization of the reset signal on a specific clock domain requires a minimum of two flops. Figure 1 shows the first flip-flop (FF1) with output Q reset to 0, and input D tied high. This flip-flop can go to a metastable state if RSTB is de-asserted near a CLK active edge. However, the second flip-flop (FF2) remains stable at 0, since the input and output are both low, preventing any output change due to the input that might occur when a reset is removed.

Figure 1. VDD-based Reset Synchronizer

Using the VDD-based reset synchronizer, you can generate the main source (arstb_main) for the asynchronous reset. The reset is typically a high fan-out net. Implement a reset tree to maintain a good fan-out load to help meet the recovery and removal checks on driven registers during de-assertion. Figure 2 shows how arstb_main is distributed to drive the asynchronous resets of the registers.

Figure 2.  arstb_main as Asynchronous Reset Source