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Ixiasoft
1.4.2.1. Coding Synchronous Reset with Follower Registers
Some registers with synchronous resets have follower registers or a pipeline immediately following, as the following example shows:
Figure 21. Resettable Flop with Register Follower
The following example shows incorrect coding for this circuit:
always @(posedge clk)
begin
if (!rstb)
data_reg[31:0] <= 32‘d0;
else
begin
data_reg[31:0] <= inp_data[31:0];
data_reg_p1[31:0] <= data_reg[31:0];
end
end
Unfortunately, the incorrect coding results in unnecessary logic, as the following figure shows:
Figure 22. Synthesized Circuit for Incorrect Register Follower Code
The incorrect coding produces unnecessary logic before the 32-bit follower register data_reg_p1. The code uses rstb as a condition to load the output of the previous register data_reg or retains its current value, which creates an unnecessary 32-bit loopback. Aside from the routing congestion that the loopback creates, this loopback limits the ability of the register data_reg_p1 from being retimed to help resolve critical path issues.
The rules are:
- Each verilog procedural block or VHDL process must model only one type of flip-flop.
- Do not combine resettable and non-resettable flip-flops in the same procedural block or process.
The following example shows proper coding for this circuit:
always @(posedge clk)
begin
if (!rstb)
data_reg[31:0] <= 32‘d0;
else
begin
data_reg[31:0] <= inp_data[31:0];
end
end
always @(posedge clk)
begin
data_reg_p1[31:0] <= data_reg[31:0];
end