AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.3.1. Example: Asynchronous Reset Design Assistant Analysis

You can use Design Assistant to identify and correct problematic asynchronous reset conditions. For this example, Figure 6 shows a circuit with two separate groups of registers, with asynchronous resets driven by the input port rstb.

Figure 6. Circuit Design with Asynchronous Reset

The following steps describe Design Assistant reset analysis of the circuit:

  1. After running the Fitter or a full compilation, view the Design Assistant reports in the Timing Analyzer report folder of the Compilation Report.
    Figure 7. Design Assistant Report in Timing Analyzer Folder of Compilation Report
  2. Review any rule violations in the report. This example shows 20 violations of rule RES-50001 – Asynchronous Resets Not Synchronized. Select RES-50001 in the list to show all instances violating the specific rule in your design.
    Figure 8. Design Assistant (Signoff) Results
  3. Find the location of rule violations in your design. You can cross probe each instance to locate the node.
    Figure 9. Locating to RES-50001 Rule Violations
  4. Identify the root cause of the violation and the recommendation for correction in the Design Assistant Recommendation.
    Figure 10. RES-50001 Rule Recommendation
  5. Implement the rule Recommendation in your design RTL. In this example, Design Assistant recommends inserting a synchronizer to feed all asynchronous reset pins the report specifies, as the following example shows.
    Note: To time the recovery and removal going to the reset pin, the clock domain of the synchronizer must match the latching domain of the register being reset.
    Figure 11. Adding a VDD-Based Reset Synchronizer
  6. Recompile the design with your changes, and rerun Design Assistant to confirm corrections. Repeat steps 1 through 6 until all issues are fixed.