AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents C-Cycle Equivalence

The c-cycle refers to the number of clock cycles a design requires after power-up to ensure functional equivalence. The c-cycle value is an important consideration in structuring the reset sequence of your design.

Consider the following simple circuit where register F1 at power-up can have either state ‘0’ or state ‘1’. Assuming the clouds of logic are purely combinational, there are 2 possible states in the circuit, F1 = ‘0’ or F1 = ‘1’.
Figure 34. Circuit Before Retiming
If the retimer pushes F1 forward, then the register is duplicated in each branch that F1 drives.
Figure 35. Register Duplicated
After retiming and register duplication, the circuit now has four possible states at power-up. The addition of two potential states in the circuit after retiming, potentially changes the deign functionality.
Table 2.  Registers F11 and F12 States
F11 States F12 States
0 0
0 1
1 0
1 1

Apply an extra clock cycle after power-up to ensure the functional equivalence of the design after retiming. The extra cycle ensures that the states of F11 and F12 are always identical resulting in two possible states for the registers, 0/0 or 1/1, assuming the combinational logic is non-inverting on both paths.

Backward retiming is always a safe operation with c-cycle value of 0. The Compiler always permits merging if you do not specify initial conditions for F11 and F12. If you specify initial conditions, the Compiler accounts for those initial states and retiming transformation occurs only if the initial states are preserved.