AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents Determining the Reset Sequence Requirement

You can view the c-cycle value in the Reset Sequence Requirement section of the Compilation Report. The report lists the number of cycles to add on a clock domain basis. The following Reset Sequence Requirement report indicates that the clk domain requires adding 10 additional cycles to the reset sequence to ensure correct functionality.

Figure 36. Reset Sequence Requirement Report

For more information about initial power-up conditions and retiming reset sequences, refer to the Intel® Hyperflex™ Architecture High-Performance Design Handbook.