AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.3. Analyzing Resets with Design Assistant

The Intel® Quartus® Prime Design Assistant is a design rule checking tool that helps you to detect and correct any violations against a standard set of Intel FPGA-recommended design guidelines. Correcting design rule violations improves the reliability, timing performance, and logic utilization of your design.

The Design Assistant includes several rule categories to help you check for functional and timing closure related reset issues. Following analysis, Design Assistant provides recommendations for correcting any violations. The following table lists the Design Assistant rule categories that help detect reset issues:

Table 1.  Design Assistant Rules Categories for Reset, Clock Domain Crossing, and Timing Closure
Categories Rule Prefix
Reset Rules RES
Clock Domain Crossing Rules CDC
Timing Closure Rules TMC

For descriptions of all rules, refer to "Design Assistant Rule Categories" in Intel Quartus Prime Pro Edition User Guide: Design Recommendations.