AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents Recovery and Removal Checks

During the de-assertion of a reset, the control to the output of a flip-flop transfers from the reset line to the clock signal, like a regular D flip-flop. To avoid the register entering metastable state, you must ensure that the reset is not de-asserted in certain time frames of the active clock edge.

In Figure 3, the Removal Time, Trem, refers to the minimum time, after the active clock edge, that the reset must be stable before being de-asserted. The reset Removal Check ensures that the de-asserted reset signal is not captured by the same clock edge that launches the reset.

Figure 3. Recovery and Removal Check Timing Diagram

Reset Recovery Time, Trec, is the minimum time between the de-assertion of a reset and the clock signal being high again. The reset Recovery Check ensures that the reset signal is stable for a minimum time after de-assertion, before the next active clock edge.

The Intel® Quartus® Prime Timing Analyzer computes recovery and removal slacks separately from set-up and hold slacks. You can find the summary and individual reports in the Timing Analyzer reports.

Figure 4.  Compilation Report Window - Timing Analyzer Reports