AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.1.2. Hyper-Registers Require Synchronous Reset

For the best performance, avoid resets except when necessary. When design conditions require a reset, you must decide the type of reset to use, asynchronous or synchronous.

The Hyper-Retiming feature facilitates movement between registers to balance the propagation delays between them, with the aim of fixing critical path timing. Hyper-Retiming moves the ALM registers into the Hyper-Register locations that are available in every routing segment of the fabric.

By design, the Hyper-Registers do not have asynchronous resets. Therefore, the Intel® Quartus® Prime Fitter cannot retime ALM registers with an asynchronous reset into a Hyper-Register location. Instead, use a synchronous reset to permit the usage of the Hyper-Registers during retiming. The ability to retime into Hyper-Registers helps achieve the best possible performance.

In blocks where the use of asynchronous resets is unavoidable, minimize the use of asynchronous resets within these blocks wherever possible. Asynchronous resets allow a circuit to reset with or without a clock signal present. There may be blocks that require this function, including any of the following:

  • Clock source and distribution circuitry
  • Power management block
  • System reset generator

Use synchronous resets if a clock is present on every reset assertion. You may be able to use asynchronous resets for blocks using slow clocks when timing is not critical, especially if the asynchronous reset helps in decongesting data path routing.