AN 917: Reset Design Techniques for Intel® Hyperflex™ Architecture FPGAs

ID 683539
Date 1/05/2021
Document Table of Contents

1.4. Implementing Reset Circuitry

Improper application of resets in your design can cause operational design failures. The following sections provide reset implementation coding techniques and examples that comply with the following implementation guidelines. Follow these guidelines to properly implement reset and obtain the best timing possible:

  • Ensure that every register that must power-up or reset to a known value connects to a reset.
  • Avoid unnecessary resets to lessen possibility of routing congestion.
  • Use synchronous resets to allow retiming into Hyper-Registers. Hyper-Registers used on retiming cannot be reset asynchronously.
  • Use a regular two register chain synchronizer for resets coming in asynchronously, before feeding them to synchronous reset pins of registers. Provide a reset synchronizer for every clock domain.
  • Use a VDD-based synchronizer for resets that connect to asynchronous reset pins. Provide a synchronizer for every clock domain.

Refer to the following topics for implementing reset circuitry: