LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
ID
683520
Date
9/20/2022
Public
Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Timing Closure Guidelines for Internal FPGA Paths
Closing timing at the internal FPGA paths is challenging for an LVDS SERDES design with high frequency and low SERDES factor.
If you observe setup violation from core registers to LVDS transmitter hardware, check the TX core registers clock parameter:
- If the parameter is set to inclock, consider changing it to tx_coreclock. Core registers that use tx_coreclock have less clock delay. Because of the PLL compensation delay on the tx_coreclock path, there is less source clock delay and more setup slack for the transfer.
- If the parameter is set to tx_coreclock, consider lowering the data rate or increasing the SERDES factor to reduce the core frequency requirement and provide more setup slack.
If you observe hold violation from the LVDS receiver to core registers, consider checking the setup slack of the transfer. If there is ample setup slack, you can attempt to over-constraint the hold for the transfer. Normally, the Fitter attempts to correct the hold violation by adding delay. Under certain circumstances, the Fitter may have calculated that adding more delay for avoiding hold violation at the fast corner can negatively affect setup at the slow corner.