LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
ID
683520
Date
9/20/2022
Public
Release Information
LVDS SERDES Intel® FPGA IP Features
LVDS SERDES IP Core Functional Modes
LVDS SERDES IP Core Functional Description
LVDS SERDES IP Initialization and Reset
LVDS SERDES Intel® FPGA IP Signals
LVDS SERDES Intel® FPGA IP Parameter Settings
LVDS SERDES Intel® FPGA IP Timing
LVDS SERDES Intel® FPGA IP Design Examples
Additional LVDS SERDES IP Core References
LVDS SERDES Intel® FPGA IP User Guide Archives
Document Revision History for LVDS SERDES Intel® FPGA IP User Guide: Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Combined LVDS SERDES IP Transmitter and Receiver Design Example
The combined transmitter and receiver design example uses your LVDS SERDES IP parameter settings and adds a complementary transmitter or receiver interface. Both interfaces are connected to the same external PLL. You can use the design example to see how to connect the transmitter and receiver interfaces.
If your LVDS SERDES IP configuration implements a transmitter, the design example adds a DPA-FIFO receiver. If your LVDS SERDES IP configuration implements any of the receiver interfaces, the design example adds a transmitter.
Figure 15. Combined LVDS SERDES Transmitter and Receiver
Generating and Using the Design Example
To generate the combined transmitter and receiver design example from the source files, run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl -system ed_synth_tx_rx
The TCL script creates a qii_ed_synth_tx_rx directory that contains the ed_synth_tx_rx.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.
For more information about make_qii_design.tcl arguments, run the following command:
quartus_sh -t make_qii_design.tcl -help