Intel® Cyclone® 10 GX Device Overview

ID 683485
Date 4/01/2019
Public
Document Table of Contents

Summary of Intel® Cyclone® 10 GX Features

Table 3.  Summary of Features for Intel® Cyclone® 10 GX Devices
Feature Description

Technology

TSMC's 20-nm process technology

Packaging

  • 1.0 mm ball-pitch FineLine BGA packaging
  • 0.8 mm ball-pitch Ultra FineLine BGA packaging
  • Multiple devices with identical package footprints for seamless migration between different FPGA densities
  • RoHS6-compliance

High-performance FPGA fabric

  • Enhanced 8-input ALM with four registers
  • Improved multi-track routing architecture to reduce congestion and improve compilation time
  • Hierarchical core clocking architecture
  • Fine-grained partial reconfiguration

Internal memory blocks

  • M20K—20-Kb memory blocks with hard error correction code (ECC), cascadable
  • Memory logic array block (MLAB)—640-bit memory, cascadable

Embedded Hard IP blocks

Variable-precision DSP

  • Native support for signal processing precision levels from 18 x 19 to 54 x 54, cascadable
  • Native support for 27 x 27 multiplier mode
  • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
  • Internal coefficient memory banks
  • Preadder/subtractor for improved efficiency
  • Additional pipeline register to increase performance and reduce power
  • Supports floating point arithmetic:
    • Perform multiplication, addition, subtraction, multiply-add, multiply-subtract, and complex multiplication.
    • Supports multiplication with accumulation capability, cascade summation, and cascade subtraction capability.
    • Dynamic accumulator reset control.
    • Support direct vector dot and complex multiplication chaining multiply floating point DSP blocks.

Memory controller

DDR3, DDR3L, and LPDDR3

PCI Express®

PCI Express (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, or x4) hard IP with complete protocol stack, endpoint, and root port.

Transceiver I/O

  • PCS hard IPs that support:
    • 10 Gbps Ethernet (10GbE) 1
    • PCIe PIPE interface
    • Interlaken
    • Gbps Ethernet (GbE)
    • 6G Common Public Radio Interface (CPRI) with deterministic latency support
    • Gigabit-capable passive optical network (GPON) with fast lock-time support
  • 12G Serial Digital Interface (SDI)
  • 8B/10B, 64B/66B, 64B/67B encoders and decoders
  • Custom mode support for proprietary protocols

Core clock networks

  • Up to 300 MHz fabric clocking, depending on the application:
    • 467 MHz external memory interface clocking with 1,866 Mbps DDR3 interface
    • 300 MHz LVDS interface clocking with 1.434 Gbps LVDS interface
  • Global, regional, and peripheral clock networks
  • Clock networks that are not used can be gated to reduce dynamic power

Phase-locked loops (PLLs)

  • High-resolution fractional synthesis PLLs:
    • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
    • Support integer mode and fractional mode
    • Fractional mode support with third-order delta-sigma modulation
  • Integer PLLs:
    • Adjacent to general purpose I/Os
    • Support external memory and LVDS interfaces

FPGA General-purpose I/Os (GPIOs)

  • One 3 V I/O bank supporting up to 3.0 V I/O standards
  • Up to 1.434 Gbps LVDS—every pair can be configured as receiver or transmitter
  • On-chip termination (OCT)
  • 1.2 V to 3.0 V single-ended LVTTL/LVCMOS interfaces using LVDS I/O or 3 V I/O banks

External Memory Interface

  • Hard memory controller—DDR3, DDR3L, and LPDDR3 support
  • DDR3 speeds up to 933 MHz/1,866 Mbps

Low-power serial transceivers

  • Continuous operating range up to 12.5 Gbps
  • Backplane support up to 6.6 Gbps
  • Extended range down to 125 Mbps with oversampling
  • ATX transmit PLLs with user-configurable fractional synthesis capability
  • Transmitter pre-emphasis and de-emphasis
  • Dynamic reconfiguration of individual transceiver channels

Configuration

  • Tamper protection—comprehensive design protection to protect your valuable IP investments
  • Enhanced 256-bit advanced encryption standard (AES) design security with authentication
  • Configuration via protocol (CvP) using PCIe Gen1 or Gen2
  • Dynamic reconfiguration of the transceivers and PLLs
  • Fine-grained partial reconfiguration of the core fabric
  • Active Serial ×4 Interface

Power management

  • Programmable Power Technology
  • Intel® Quartus® Prime Pro Edition integrated power analysis tool

Software and tools

  • Intel® Quartus® Prime Pro Edition design suite
  • Transceiver toolkit
  • Platform Designer (Standard) system integration tool
  • DSP Builder advanced blockset
  • OpenCL* support
1 10GBASE-KR is not supported.

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