PCIe Gen1 and Gen2 Hard IP
Intel® Cyclone® 10 GX devices contain PCIe hard IP that is designed for performance and ease-of-use:
- Includes all layers of the PCIe stack—transaction, data link and physical layers.
- Supports PCIe Gen2 Endpoint and Root Port in x1, x2, or x4 lane configuration5.
- Operates independently from the core logic—optional configuration via protocol (CvP) allows the PCIe link to power up and complete link training in less than 100 ms while the Intel® Cyclone® 10 GX device completes loading the programming file for the rest of the FPGA.
- Provides improved end-to-end datapath protection using ECC.
- Supports FPGA configuration via protocol (CvP) using PCIe at Gen2 or Gen1 speed.
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