External Memory Interface
The memory interface within Intel® Cyclone® 10 GX FPGAs delivers the highest performance and ease of use. You can configure up to a maximum width of 72 bits when using the hard memory controllers.
Each I/O contains a hardened DDR read/write path (PHY) capable of performing key memory interface functionality such as read/write leveling, FIFO buffering to lower latency and improve margin, timing calibration, and on-chip termination.
The timing calibration is aided by the inclusion of hard microcontroller based on Intel's Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Intel® Cyclone® 10 GX device to compensate for any changes in process, voltage, or temperature either within the Intel® Cyclone® 10 GX device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.
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