Cyclone® 10 GX Device Overview

ID 683485
Date 4/01/2019
Document Table of Contents

Enhanced Configuration and Configuration via Protocol

Table 15.  Configuration Schemes and Features of Intel® Cyclone® 10 GX Devices Intel® Cyclone® 10 GX devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width

Max Clock Rate


Max Data Rate


Decompression Design Security8 Partial Reconfiguration 9 Remote System Update
JTAG 1 bit 33 33 Yes 10
Active Serial (AS) through the EPCQ-L configuration device

1 bit,

4 bits

100 400 Yes Yes Yes10 Yes
Passive serial (PS) through CPLD or external microcontroller 1 bit 100 100 Yes Yes Yes10 Parallel Flash Loader (PFL) IP core
Fast passive parallel (FPP) through CPLD or external microcontroller 8 bits 100 3200 Yes Yes Yes11 PFL IP core
16 bits Yes Yes
32 bits Yes Yes
Configuration via Protocol [CvP (PCIe*)]

x1, x2, x4 lanes

5000 Yes Yes Yes10

You can configure Intel® Cyclone® 10 GX devices through PCIe using Configuration via Protocol (CvP). The Intel® Cyclone® 10 GX CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

7 Enabling either compression or design security features affects the maximum data rate. Refer to the Intel® Cyclone® 10 GX Device Datasheet for more information.
8 Encryption and compression cannot be used simultaneously.
9 Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Intel® for support.
10 Partial configuration can be performed only when it is configured as internal host.
11 Supported at a maximum clock rate of 100 MHz.