Intel® Cyclone® 10 GX Device Overview

ID 683485
Date 4/01/2019
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PMA Features

Intel® Cyclone® 10 GX transceivers provide exceptional signal integrity at data rates up to 12.5 Gbps. Clocking options include ultra-low jitter ATX PLLs (LC tank based), clock multiplier unit (CMU) PLLs, and fractional PLLs.

Each transceiver channel contains a channel PLL that can be used as the CMU PLL or clock data recovery (CDR) PLL. In CDR mode, the channel PLL recovers the receiver clock and data in the transceiver channel.

Table 12.  PMA Features of the Transceivers in Intel® Cyclone® 10 GX Devices

Feature

Capability

Chip-to-Chip Data Rates

125 Mbps to 12.5 Gbps

Backplane Support Drive backplanes at data rates up to 6.6 Gbps

Optical Module Support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4

Cable Driving Support

SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis

4-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear Equalizer (CTLE)

High-gain linear receive equalization to compensate for system channel loss

Variable Gain Amplifier Optimizes the signal amplitude prior to the CDR sampling and operates in fixed and adaptive modes

Precision Signal Integrity Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on power-up, which provides the optimal signal integrity and jitter performance

Advanced Transmit (ATX) PLL

Low jitter ATX (LC tank based) PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols

Fractional PLLs

On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost

Digitally Assisted Analog CDR

Superior jitter tolerance with fast lock time

Dynamic Reconfiguration

Allows independent control of the Avalon memory-mapped interface of each transceiver channel for the highest transceiver flexibility

Multiple PCS-PMA and PCS-PLD interface widths

8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width, encoding, and reduced latency

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