Cyclone® 10 GX Device Overview

Download PDF
ID 683485
Date 4/01/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Overview
Intel® Cyclone® 10 GX Device Overview x
Key Advantages of Intel® Cyclone® 10 GX Devices Summary of Intel® Cyclone® 10 GX Features Intel® Cyclone® 10 GX Available Options Intel® Cyclone® 10 GX Maximum Resources Intel® Cyclone® 10 GX Package Plan I/O Vertical Migration for Intel® Cyclone® 10 GX Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1 and Gen2 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Cyclone® 10 GX Device Overview
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Cyclone® 10 GX Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Cyclone® 10 GX Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Cyclone® 10 GX Device Overview

Transceiver Channels

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
  • The PMA provides primary interfacing capabilities to physical channels.
  • The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have 6 channels. There are some transceiver banks that contain only 4 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a highly configurable clock distribution network.

Figure 5. Device Chip Overview for Intel® Cyclone® 10 GX DevicesThis figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for flip chip packages. Different Intel® Cyclone® 10 GX devices may have different floorplans than the one shown in this figure.


Level Two Title