Intel® Cyclone® 10 GX Device Overview

ID 683485
Date 4/01/2019
Public
Document Table of Contents

Transceiver Channels

All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
  • The PMA provides primary interfacing capabilities to physical channels.
  • The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.

A transceiver channel consists of a PMA and a PCS block. Most transceiver banks have 6 channels. There are some transceiver banks that contain only 4 channels.

A wide variety of bonded and non-bonded data rate configurations is possible using a highly configurable clock distribution network.

Figure 5. Device Chip Overview for Intel® Cyclone® 10 GX DevicesThis figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for flip chip packages. Different Intel® Cyclone® 10 GX devices may have different floorplans than the one shown in this figure.


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