In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them, it makes it easier to close timing.
You can use the I/O PLLs for general purpose applications in the core such as clock network delay compensation and zero-delay buffering.
Intel® Cyclone® 10 GX devices support PLL-to-PLL cascading.
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