Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Document Table of Contents
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3.7. 855873: An Eviction Might Overtake a Cache Clean Operation


The Cortex-A53 MPCore* processor supports instructions for cache clean operations. To avoid data corruption, the processor must ensure correct ordering between evictions and cache clean operations for the same address.

Because of this erratum, the processor can issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. The processor can also issue transactions that become outstanding in the interconnect at the same time. This situation violates the AXI Coherency Extensions (ACE) protocol specification.

This erratum occurs when the following conditions are met:
  1. One or both of the following are true:
    • L2ACTLR[14] is set to 1. This setting allows WriteEvict transactions on the ACE interface when the processor evicts data that it holds in the UniqueClean state.
    • L2ACTLR[3] is set to 0. This setting allows Evict transactions on the ACE interface when the processor evicts clean data.
  2. A CPU executes a cache clean-by-address operation for a line that is present and dirty in the L2 cache.
  3. A CPU performs any type of memory access to the same set. Memory access types can include a pagewalk, instruction fetch, cache maintenance operation or data access.
  4. An instruction fetch to the same set triggers an L2 cache eviction.
  5. A present and dirty cache line that is selected for L2 cache eviction at the same time it is targeted for a cache clean operation.


Because of this erratum transactions are erroneously reordered in the interconnect, resulting in data corruption.


You can workaround this erratum by changing the cache clean-by-address operations to cache clean-and-invalidate operations. To enable these operations, set CPUACTLR.ENDCCASCI to 1.


Category 2