Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Public
Document Table of Contents

3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment

Description

The Embedded Trace Macrocell (ETMv4) architecture requires that when a trace flush is requested on the AMBA* Trace Bus (ATB), a Cortex-A53 MPCore* processor must complete any packets that are in the process of being encoded and output them prior to acknowledging the flush request. When trace is enabled, the Cortex-A53 MPCore* processor attempts to combine multiple direct branch instructions into a single atom packet. If a direct branch instruction is executed, and an atom packet is in the process of being generated, the processor does not force completion of the packet prior to acknowledging the flush request. This erratum is a violation of the ETMv4 architecture.

The following conditions are required for this erratum to occur:

  1. ETM is enabled.
  2. Instruction tracing is active.
  3. The processor executes one or more direct branch instructions.
  4. An atom packet is in the process of being encoded but is not complete.
  5. A trace flush is requested on the AMBA* ATB.

Impact

When the above conditions occur, the ETM must complete encoding and output the atom packet prior to the trace flush request being acknowledged. Because of this erratum, the atom packet is output after the flush is acknowledged. Therefore, it appears to software monitoring the trace that the direct branch was executed after the requested flush.

Workaround

Enabling the timestamp by setting the TS bit in the Trace Configuration (TRCCONFIGR) register resolves the erratum because the atom packets complete when timestamp behavior is enabled.

Category

Category 3

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