Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Public
Document Table of Contents

3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output

Description

When the AFVALID signal on the Advanced Trace Bus (ATB) interface asserts, the ETM immediately outputs all buffered trace. The ETM must assert the AFREADY output one cycle after all trace that was buffered on the cycle in which AFVALID was first asserted.

Because of this erratum, the AFREADY signal may be asserted before all the necessary trace has been output.

Impact

Because of this erratum, the ETM may contain trace data that was generated before the flush request.

Workaround

The system can ensure that all trace has been drained from the ETM by disabling it. You can disable the ETM by clearing the TRCPRGCTLR.EN bit. Next, system software must poll the TRCSTATR.IDLE bit until it reads as 1. This value indicates the ETM is idle and all trace that was generated before the write to TRCPRGCTLR has been output.

Category

Category 3

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