3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN
Software executing at EL2 can set the HDCR.HPMN and MDCR_EL2.HPMN field to restrict non-secure EL0 and EL1 software from accessing a subset of the performance counters. If n > HPMN, then Performance Counter n (PMEVCNTR<n>) register is not accessible to non-secure EL0 or EL1. Because of this erratum, Cortex-A53 reads of inaccessible registers might not return zero as expected, but instead might read the actual contents of the counter registers.
- The processor is executing at non-secure EL1 or EL0.
- HDCR.HPMN and MDCR_EL2.HPMN are set to a value n, where n < 6.
- A read of PMEVCNTR<n> and PMEVCNTR<n>_EL0 is executed.
If the conditions described above are met, then non-secure EL0 and EL1 software can read the values of performance counters reserved for EL2.
Software executing at EL2 can set the HDCR.TPM and MDCR_EL2.TPM bit. This configuration causes all non-secure EL0 and EL1 accesses to performance monitor registers to trap to EL2. The EL2 software can then emulate accesses as required, and can mask out accesses to reserved registers.