Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Document Table of Contents

3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set


The Arm* v8 architecture requires that when all associated stages of translation are disabled for the current exception level, software only perform instruction fetches within the same or next translation granule as an instruction which has been or can be fetched due to sequential execution. In the conditions detailed below, this erratum may cause the Cortex-A53 MPCore* processor to access other locations speculatively due to instruction fetches.

For this erratum to occur:
  • The CPU must be executing at EL3, EL2 or Secure EL1.
  • The CPU can be in either AArch32 or AArch64 execution state.
  • Address translation is disabled for the current exception level (by clearing the appropriate SCTLR.M, HSCTLR.M or SCTLR_ELx.M bit).
  • The HCR.VM or HCR_EL2.VM bit is set.


If the above conditions are met, then speculative instruction fetches may be made to memory locations not permitted by the architecture.


Because the HCR.VM bit default reset value is low, this situation is most likely to occur in power down code, if EL2 or EL3 software disables address translation before the core is powered down. To work around this erratum, software must clear the HCR.VM bit before disabling address translation at EL3, EL2 or Secure EL1.


Category 2