Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Public
Document Table of Contents

3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results

Description

When the Cortex-A53 MPCore* processor is executing in the AArch64 state, certain sequences of instructions that include AES instructions may cause incorrect results.

There are two code sequences that can cause this erratum in the AArch64 execution state:

  • Code sequence 1:
    1. The CPU executes an AESE instruction.
    2. The CPU executes a USQADD instruction.
      • Both the Vn and Vd of this instruction must be the same register as Vd for the AES instruction.
      • The size field for this instruction must be '00', indicating byte-sized elements.
      • The USQADD instruction can be in either vector or scalar form.
  • Code sequence 2:
    1. The CPU executes a SUQADD instruction.
      • The size field for this instruction must be 00, indicating byte-sized elements.
      • The SUQADD instruction can be in either vector or scalar form.
    2. The CPU executes an AESMC or AESIMC instruction.
      • Both the Vn and Vd of this instruction must be the same register as the Vd for the SUQADD instruction.
For both these sequences, the two instructions listed must be executed consecutively, with no other instructions or exceptions between them. If either of these sequences is met, the final result of the affected instruction sequence may be incorrect.

Impact

The sequences of instructions described in the conditions above are not expected to occur in real code because they do not perform useful computation. Therefore, there is no impact expected to real systems.

Workaround

Because the code sequences for this erratum are not expected to occur in real code, no workaround is required.

Category

Category 3

Did you find the information on this page useful?

Characters remaining:

Feedback Message