Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Public
Document Table of Contents

2.3.1. HPS Stops on the First Read Request to SDRAM

Description

If the Intel® Stratix® 10 HPS External Memory Interface (EMIF) is enabled in DDR x32 or x16 mode with or without ECC (IO48 Banks 2M/2N), and the IO48 Bank 2L is being used by the core fabric in specific use cases such as:
  • LVDS with Dynamic Phase Alignment (DPA)
  • LVDS without DPA and with Clock Phase Alignment (CPA) engaged
  • Fabric-EMIF
  • PHYLite
then the HPS stops on the first read request to SDRAM, and cannot be recovered.

Workaround

When using the Intel® Stratix® 10 HPS EMIF in DDR x32 or DDR x16 configuration with or without ECC (IO48 Banks 2M, 2N), the IO48 Bank 2L can only be used for LVDS without DPA and without CPA engaged, or GPIO purposes. All other banks have no restrictions and they can be used for LVDS, or Fabric-EMIF, or PHYLite, or GPIO.

Status

Affects:
  • Intel® Stratix® 10 TX 850
  • Intel® Stratix® 10 TX 1100
  • Intel® Stratix® 10 TX 2500
  • Intel® Stratix® 10 TX 2800

Status: No planned fix

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