Intel® Stratix® 10 TX Device Errata

ID 683470
Date 7/21/2022
Public
Document Table of Contents

3.12. 851672: ETM May Trace an Incorrect Exception Address

Description

The address in an exception packet is the preferred exception return address. Because of this erratum, the address may be equal to the target address of the exception. The trace stream is not corrupted, and decompression can continue after the affected packet.

The following sequence is required for this erratum to occur:

  1. The ETM must start tracing instructions because of one of the following:
    1. ViewInst starts.
    2. The security state changes indicating trace is now permitted.
    3. The values of the external debug interface (DBGEN, SPIDEN, NIDEN, SPNIDEN) change to indicate trace is now permitted.
    4. The CPU exits debug mode.
  2. Before the CPU executes any other behavior that causes a trace to be generated, it executes a direct branch instruction, which may or may not be taken.
  3. The next instruction is a load or store that causes a data abort or watchpoint exception.
After this sequence, provided certain timing specific conditions are met, the address in the exception packet may be incorrect.

Impact

The trace decompressor may incorrectly infer execution of many instructions from the branch target to the provided address.

Workaround

The trace decompressor can detect that this erratum has occurred by checking if the exception address is in the vector table and identifying if the branch was not expected to be taken to the vector table. A decompressor can infer the correct address of the exception packet. The target of the preceding branch (if the branch was taken), or the next instruction after the branch (if the branch was not-taken) provides the correct address of the exception packet.

Category

Category 3

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