Vision Processing with the Canny Edge Detection Reference Design
ID
683433
Date
2/14/2015
Public
1.1. About Canny Edge Detection
1.2. About the Canny Edge Detection Reference Design
1.3. Getting Started with the Canny Edge Reference Design
1.4. Canny Edge Detection Reference Design Block Description
1.5. Stream-to-Memory Conversion
1.6. Latency and Throughput
1.7. Canny Edge Reference Design Resource Usage
1.3.1. Hardware and Software Requirements
1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design
1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image
1.3.4. Canny Edge Reference Design Initial Startup Problems
1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design
1.3.6. Capturing the Pixel Stream
1.3.7. Programming the FPGA with the Canny Edge Reference Design
1.3.8. Initializing the ARM Processor
1.5. Stream-to-Memory Conversion
The Canny edge reference design FPGA processing architecture is stream based: an output pixel is produced for every input pixel. Edge-linking is memory based: an entire video frame is available in memory for processing. The design implements a stream to memory conversion to reorder the FPGA pixel stream into a proper video frame in memory for the ARM processor. After the ARM processes an entire video frame, the design streams it from memory to the FPGA for the output monitors to receive pixel streams.
Figure 7. Clock Domains