Vision Processing with the Canny Edge Detection Reference Design

ID 683433
Date 2/14/2015
Document Table of Contents

1.5. Stream-to-Memory Conversion

The Canny edge reference design FPGA processing architecture is stream based: an output pixel is produced for every input pixel. Edge-linking is memory based: an entire video frame is available in memory for processing. The design implements a stream to memory conversion to reorder the FPGA pixel stream into a proper video frame in memory for the ARM processor. After the ARM processes an entire video frame, the design streams it from memory to the FPGA for the output monitors to receive pixel streams.
Figure 7. Clock Domains

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