Visible to Intel only — GUID: dmi1421329940002
Ixiasoft
Visible to Intel only — GUID: dmi1421329940002
Ixiasoft
1.5.1. FPGA and ARM Processor Clock Domains
The Qsys components are in the fixed FPGA 50 MHz clock domain. The design uses digital video interface (DVI) and its clock frequency varies according to video resolution. Because the pixel streams are in the clk_dvi domain, the design uses a dual clocked FIFO buffer for proper data clock domain bridging. Using a FIFO buffer buffers the pixel data.
The FPGA pixel stream is not continuous as it pauses when the data enable signal is active low. For DVI, pixel data are only latched when the DE control signal is active high. Furthermore, the mSGDMA operates using burst transactions as the HPS SDRAM multiport front end (MPFE) controller may be busy servicing other requests. For example when the ARM processor reads or writes from memory. Hence, a buffer ensures that no pixel data is lost. The design allows no backpressure to occur. For the stream-to-memory FIFO clock domain bridging buffer, the fill rate is determined by the input pixel stream out of the FPGA Canny double threshold block. The output rate is determined by the mSGDMA stream to memory transaction rate.