Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.5.4. Operating System and Video Driver

The Canny edge reference design operating system (OS) provides important function calls such as file read and write that the design uses to export important information, such as a frame dump, out of the ARM processor via Ethernet. The design implements the entire Ethernet stack in the OS for communication with the ARM processor.

The frame buffer resides in the physical address space. To access this data in userspace, map the physical address space of the frame buffer to the user address space. A user-space device driver accesses the in-built Linux kernel module /dev/mem to execute the physical to user-space address mapping. This driver is based on Linux’s Windows X server real-time video driver. The custom written user-space device driver also provides easy application programming interface (API) function calls for the programmer to read and write a video frame: 

 while(1){//vid1 is video handle returned by driver 
get_vframe(&vid1,storage,get_fPixCount(&vid1)); //Get 1 stable input video frame 
edge_link(storage,get_fLength(&vid1),get_fPixCount(&vid1)); //Perform image processing on 1 video frame 
dump_vframe(&vid1,storage,get_fPixCount(&vid1)); //Output 1 video frame} //Loop for continuous video processing

The driver handles all control signaling and data transfer to/from the FPGA hardware. The user-space device driver also provides a simple function to continuously measure the average output frame rate dynamically.

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