Vision Processing with the Canny Edge Detection Reference Design

ID 683433
Date 2/14/2015
Public
Document Table of Contents

1.4. Canny Edge Detection Reference Design Block Description

Figure 1. Block Diagram

The design matches the output pixel rate to the input pixel rate, easily achieving real time requirements of 60 fps. However, the maximum frequency (fMAX) of the individual blocks limits the maximum video input resolution. Implementing most of the Canny algorithm on the FPGA offloads the ARM processor from repetitive and time consuming mathematical operations. Thus, the ARM processor engages in more complicated, upstream, higher value image processing algorithms. For example, the design implements the last Canny edge linking block in the ARM processor because it is a recursive variable depth algorithm that cannot be unrolled.

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