Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.4. Canny Edge Detection Reference Design Block Description

Figure 1. Block Diagram

The design matches the output pixel rate to the input pixel rate, easily achieving real time requirements of 60 fps. However, the maximum frequency (fMAX) of the individual blocks limits the maximum video input resolution. Implementing most of the Canny algorithm on the FPGA offloads the ARM processor from repetitive and time consuming mathematical operations. Thus, the ARM processor engages in more complicated, upstream, higher value image processing algorithms. For example, the design implements the last Canny edge linking block in the ARM processor because it is a recursive variable depth algorithm that cannot be unrolled.

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