Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image

  1. Write the reference design SD card image to a microSD card: 
    #sudo dd if=Canny_sdcard_image of=/dev/sdx bs=1M
#sudo sync

    After a successful Linux boot, the FPGA image automatically loads.

  2. Set the DIP switches to select the output from one of the Canny blocks. If there is no video output, disconnect the DVI source cable from the BITEC card, reconnect the DVI source cable wire.
    Table 1.  DIP Switch Settings
    FPGA DIP Switch configuration (3,2,1,0) Monitor Output
    3 2 1 0
    OFF OFF OFF ON Colour
    OFF OFF OFF OFF Grayscale
    OFF OFF ON OFF Sobel
    OFF ON OFF OFF NMS
    ON OFF OFF OFF Double Threshold
    ON ON OFF OFF ARM output
    ON ON ON OFF Approximated 45 degree edge angle colour coded output
    OFF OFF ON ON Blue color channel only
    OFF ON OFF ON Green color channel only
    ON OFF OFF ON Red color channel only
  3. Type root to login. You do not need a password.
  4. Press the FPGA 0 push button to activate the ARM frame reader. FPGA LED 3 illuminates.
  5. Press FPGA 1 push button to activate the ARM frame writer. FPGA LED 2 illuminates.

    The frame reader and writer cannot be running during the boot process.

  6. Navigate to the altera folder, and type ./edge_link into the terminal to start the edge linking program.
    Table 2.  Files in /altera Directory
    File name Description Example use
    edge_link Edge linking program for Canny edge detection ./edge_link
    dumpram Dumps an image frame into the Linux filesystem ./dumpram
    pass_thru Does a simple ARM video loop through without any processing ./pass_thru
    devmem3 Tool to peak and poke the physical memory contents in the ARM processor

    ./devmem3 r 0xff200000 0x0

    (Read, Physical address, Address offset)

    ./devmem3 w 0xff200000 0x0 0x1

    (Read, Physical address, Address offset, write value)
    burn_fpga Script to program the FPGA from Linux

    ./burn_fpga canny_fpga.rbf
    gator.ko

    Linux kernel module for ARM DS5 streamline

    Note: Only works for v3.9.0

    		 insmod gator.ko
    gatord Linux kernel daemon for ARM DS5 streamline Linux profiling ./gatord.ko&
  7. If image is not centred on the monitor, press the CPU reset button and repeat from #dmi1421333866870.xml/step_N1018C_N10011_N1000E_N10001.
Level Two Title