Vision Processing with the Canny Edge Detection Reference Design

ID 683433
Date 2/14/2015
Public
Document Table of Contents

1.5.2. HPS SDRAM Partitions

The Canny edge reference design uses the HPS SDRAM to boost data throughput and improve processing time.

Getting the frame data from the FPGA SDRAM via the FPGA-ARM AXI connection bus requires no overheads.. The design runs a Linux operating system on the ARM processor and it partitions the HPS SDRAM to provide mutually exclusive access for the FPGA and the ARM processor. The design does not allow the FPGA to write into the Linux address space, which may cause Linux to crash during run-time. The design assigns the top 512 MB of the HPS SDRAM to Linux; the bottom 512 MB for private access by the FPGA for frame buffering.

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