Vision Processing with the Canny Edge Detection Reference Design
ID
683433
Date
2/14/2015
Public
1.1. About Canny Edge Detection
1.2. About the Canny Edge Detection Reference Design
1.3. Getting Started with the Canny Edge Reference Design
1.4. Canny Edge Detection Reference Design Block Description
1.5. Stream-to-Memory Conversion
1.6. Latency and Throughput
1.7. Canny Edge Reference Design Resource Usage
1.3.1. Hardware and Software Requirements
1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design
1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image
1.3.4. Canny Edge Reference Design Initial Startup Problems
1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design
1.3.6. Capturing the Pixel Stream
1.3.7. Programming the FPGA with the Canny Edge Reference Design
1.3.8. Initializing the ARM Processor
1.5.2. HPS SDRAM Partitions
The Canny edge reference design uses the HPS SDRAM to boost data throughput and improve processing time.
Getting the frame data from the FPGA SDRAM via the FPGA-ARM AXI connection bus requires no overheads.. The design runs a Linux operating system on the ARM processor and it partitions the HPS SDRAM to provide mutually exclusive access for the FPGA and the ARM processor. The design does not allow the FPGA to write into the Linux address space, which may cause Linux to crash during run-time. The design assigns the top 512 MB of the HPS SDRAM to Linux; the bottom 512 MB for private access by the FPGA for frame buffering.