Vision Processing with the Canny Edge Detection Reference Design

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ID 683433
Date 2/14/2015
Public
Document Table of Contents
Document Table of Contents x
1. Vision Processing with the Canny Edge Detection Reference Design
1. Vision Processing with the Canny Edge Detection Reference Design x
1.1. About Canny Edge Detection 1.2. About the Canny Edge Detection Reference Design 1.3. Getting Started with the Canny Edge Reference Design 1.4. Canny Edge Detection Reference Design Block Description 1.5. Stream-to-Memory Conversion 1.6. Latency and Throughput 1.7. Canny Edge Reference Design Resource Usage
1.3. Getting Started with the Canny Edge Reference Design x
1.3.1. Hardware and Software Requirements 1.3.2. Connecting the Hardware to Use the Canny Edge Reference Design 1.3.3. Loading the Canny Edge Reference Design FPGA Image with the SD Card Image 1.3.4. Canny Edge Reference Design Initial Startup Problems 1.3.5. Controlling the FPGA Flow of the Canny Edge Reference Design 1.3.6. Capturing the Pixel Stream 1.3.7. Programming the FPGA with the Canny Edge Reference Design 1.3.8. Initializing the ARM Processor
1.4. Canny Edge Detection Reference Design Block Description x
1.4.1. Greyscale Conversion 1.4.2. Gaussian Blurring 1.4.3. Sobel Edge Intensity 1.4.4. Nonmaximal Suppression 1.4.5. Double Threshold 1.4.6. Edge Linking
1.5. Stream-to-Memory Conversion x
1.5.1. FPGA and ARM Processor Clock Domains 1.5.2. HPS SDRAM Partitions 1.5.3. Frame Buffering 1.5.4. Operating System and Video Driver 1.5.5. About the Edge-linking Algorithm
1. Vision Processing with the Canny Edge Detection Reference Design

1.3.8. Initializing the ARM Processor

Initialize the ARM processor, if the FPGA is not configured during U-boot.
  1. Program the FPGA using the Quartus II software or the burn_fpga tool after the ARM boot process completes.
  2. Press the WARM reset button to reboot Linux without erasing the loaded FPGA design, which initializes the FPGA HPS SDRAM interface correctly. Only initialize it during the boot process with an FPGA image running.
  3. If using Altera’s GSRD Linux Distro, kill the scroll server application, which may interfere with the frame reader and writer
    1. Type ps to get a list of the currently running processes.
    2. Find the process ID number of the scroll server application.
    3. Kill scroll server by typing kill <PID number>
  4. Press the FPGA 0 Push button to activate the ARM Frame reader.
    FPGA LED 3 illuminates.
  5. Press FPGA 1 push button to activate the ARM frame writer.
    The Frame reader and writer cannot be running during the boot process. If synchronization is off, press the CPU reset button and repeat from step 4.
    FPGA LED 2 illuminates.
Level Two Title