3.1.27.5. create_clock (::quartus::sdc)

Intel® Quartus® Prime Pro Edition User Guide: Scripting

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ID 683432

Date 12/13/2021

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3.1.27.5. create_clock (::quartus::sdc)

The following table displays information for the create_clock Tcl command:

Tcl Package and Version	Belongs to ::quartus::sdc
Syntax	`create_clock [-h \| -help] [-long_help]` `[-add]` `[-name` <clock_name> `]` `-period` <value> `[-waveform` <edge_list> `]` `[` <targets> `]`
Arguments	`-h \| -help`	Short help
	`-long_help`	Long help with examples and possible return values
	`-add`	Adds clock to a node with an existing clock
	`-name` <clock_name>	Clock name of the created clock
	`-period` <value>	Speed of the clock in terms of clock period
	`-waveform` <edge_list>	List of edge values
	<targets>	List or collection of targets
Description	Defines a clock. If the -name option is not used, the clock name is the same as the first target in the list or collection. The clock name is used to refer to the clock in other commands. The -period option specifies the clock period. It is also possible to use this option to specify a frequency to define the clock period. This can be done by using -period option followed by either <frequency>MHz or "<frequency> MHz". However, this is a Timing Analyzer-only extension and makes the SDC syntax non-standard. The -waveform option specifies the rising and falling edges (duty cycle) of the clock, and is specified as a list of two time values: the first rising edge and the next falling edge. The rising edge must be within the range [0, period]. The falling edge must be within one clock period of the rising edge. The waveform defaults to (0, period/2). If a clock with the same name is already assigned to a given target, the create_clock command will overwrite the existing clock. If a clock with a different name exists on the given target, the create_clock command will be ignored unless the -add option is used. The -add option can be used to assign multiple clocks to a pin or port. If the target of the clock is internal (i.e. not an input port), the source latency is zero by default. If a clock is on a path after another clock, then

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Intel® Quartus® Prime Pro Edition User Guide: Scripting

3.1.27.5. create_clock (::quartus::sdc)