Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 12/13/2021
Public

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3.1.27.21. set_clock_latency (::quartus::sdc)

The following table displays information for the set_clock_latency Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc

Syntax set_clock_latency [-h | -help] [-long_help] [-clock <clock_list> ] [-early] [-fall] [-late] [-rise] -source <delay> <targets>
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-clock <clock_list> Valid clock destinations (string patterns are matched using Tcl string matching)
-early Specifies the early clock latency
-fall Specifies the falling transition clock latency
-late Specifies the late clock latency
-rise Specifies the rising transition clock latency
-source Specifies the source clock latency
<delay> Latency delay value
<targets> Valid destinations (string patterns are matched using Tcl string matching)
Description
Specifies clock latency for a given clock or clock
target.

There are two types of latency: network and
source. Network latency is the clock network delay
between the clock and register clock pins. Source
latency is the clock network delay between the clock
and its source (e.g., the system clock or base clock
of a generated clock).

The Timing Analyzer automatically computes
network latencies for all register and generated
clocks. Overriding clock network latencies is not
supported by the Timing Analyzer. Therefore, the
-source option must always be specified.

You can apply clock latency to a clock, which affects
all targets of the clock, or to a specific clock
target. If you specify a specific clock target that is
driven by more than one clock, use the -clock option
to specify which clock to use.Latencies assigned to a
clock target override any latencies assigned to a
clock.

Different clock latencies can be specified for early
(-early) and late (-late) latencies, as well as for
rising edges (-rise) and falling edges (-fall). If
only some combinations are specified, the other
combinations are used by default. For example, if only
a -rise -early latency and a -fall -early latency are
specified, then the -rise -late latency is assumed to
be the same as the -rise -early latency and the -fall
-late latency is assumed to be the same as the -fall
-early latency. If neither -rise nor -fall are used or
neither -early nor -late are used, then the latency
applies to both conditions.

Source latency can also be assigned to generated
clocks. This may be useful for specifying board level
delays from a clock output port to a clock input port
when the clock input port is acting as a feedback
clock.

The value of the targets is either a collection or a
Tcl list of wildcards used to create a collection of
the appropriate type. The values used must follow
standard Tcl or Timing Analyzer-extension substitution
rules. See help for the use_timing_analyzer_style_escaping
command for details.
Example Usage
create_clock -name SYSCLK -period 10.000 [get_ports inclk]
create_generated_clock -name OUTCLK -divide_by 1 -source [get_ports inclk] [get_ports outclk]
create_generated_clock -name FDBKCLK -divide_by 1 -source [get_ports outclk] [get_ports fdbkclk]

# Apply a simple 2.000 ns source latency to the system clock.
set_clock_latency -source 2.000 [get_clocks SYSCLK]

# Specify feedback clock latencies between output port outclk
# and the input port fdbkclk.
set_clock_latency -source -late -rise 0.800 [get_clocks FDBKCLK]
set_clock_latency -source -late -fall 0.750 [get_clocks FDBKCLK]
set_clock_latency -source -early -rise 0.500 [get_clocks FDBKCLK]
set_clock_latency -source -early -fall 0.460 [get_clocks FDBKCLK]
Return Value Code Name Code String Return
TCL_OK 0 INFO: Operation successful
TCL_ERROR 1 ERROR: Timing netlist does not exist. Use create_timing_netlist to create a timing netlist.

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