Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

3.1.28.2. derive_pll_clocks (::quartus::sdc_ext)

The following table displays information for the derive_pll_clocks Tcl command:

Tcl Package and Version

Belongs to ::quartus::sdc_ext

Syntax derive_pll_clocks [-h | -help] [-long_help] [-create_base_clocks] [-use_net_name]
Arguments -h | -help Short help
-long_help Long help with examples and possible return values
-create_base_clocks Creates base clocks on input clock ports of the design that are feeding the PLL
-use_net_name Use net names as clock names
Description
NOTE: This command is no longer supported for Stratix 10 and later families.

Identifies PLLs or similar resources in the design and creates
generated clocks for their output clock pins. Multiple generated
clocks may be created for each output clock pin if the PLL is using
clock switchover, one for the inclk[0] input clock pin and one for the
inclk[1] input clock pin.

By default this command does not create base clocks on input clock
ports that are driving the PLL. When you use the create_base_clocks
option, derive_pll_clocks also creates the base clock on an input
clock