Intel® Quartus® Prime Pro Edition User Guide: Scripting

ID 683432
Date 12/13/2021

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Document Table of Contents

3.1.27. ::quartus::sdc

The following table displays information for the ::quartus::sdc Tcl package:

Tcl Package and Version ::quartus::sdc 1.5
Synopsys Design Constraint (SDC) format is used to specify the design
intent, including the timing and area constraints of the design.
The Timing Analyzer only implements the set of SDC commands
required to specify the timing constraints of the design. For area
constraints, the QSF file should be used.

This package implements the SDC Spec Version 1.5 (June 2005).

Any command in this package can be specified in a Timing Analyzer SDC
This package is loaded by default in the following executable:


This package is available for loading in the following executable:

Tcl Commands
all_clocks (::quartus::sdc)
all_inputs (::quartus::sdc)
all_outputs (::quartus::sdc)
all_registers (::quartus::sdc)
create_clock (::quartus::sdc)
create_generated_clock (::quartus::sdc)
derive_clocks (::quartus::sdc)
get_cells (::quartus::sdc)
get_clocks (::quartus::sdc)
get_nets (::quartus::sdc)
get_pins (::quartus::sdc)
get_ports (::quartus::sdc)
remove_clock_groups (::quartus::sdc)
remove_clock_latency (::quartus::sdc)
remove_clock_uncertainty (::quartus::sdc)
remove_disable_timing (::quartus::sdc)
remove_input_delay (::quartus::sdc)
remove_output_delay (::quartus::sdc)
reset_design (::quartus::sdc)
set_clock_groups (::quartus::sdc)
set_clock_latency (::quartus::sdc)
set_clock_uncertainty (::quartus::sdc)
set_disable_timing (::quartus::sdc)
set_false_path (::quartus::sdc)
set_input_delay (::quartus::sdc)
set_input_transition (::quartus::sdc)
set_max_delay (::quartus::sdc)
set_max_time_borrow (::quartus::sdc)
set_min_delay (::quartus::sdc)
set_multicycle_path (::quartus::sdc)
set_output_delay (::quartus::sdc)