Video and Vision Processing Suite Intel® FPGA IP User Guide

Download PDF
ID 683329
Date 9/30/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Warp IP Registers

As the software API allows you to program and control the warp IP, it only has a limited set of registers.
Table 66.  Warp IP RegistersThese registers are all read-only and allow interrogation of the Warp IP’s parameter settings. All the registers are 32-bit wide.
Register Name Offset Address Access Type Description
vid_pid 0x000 RO Warp IP product and vendor ID
version_number 0x004 RO The version for this release of the Warp IP
Reserved 0x008 RO
Reserved 0x00C RO
pip 0x010 RO Indicates value of pixels in parallel parameter
color_planes 0x014 RO Indicates value of number of color planes parameter
cps 0x018 RO Indicates value of bits per color sample parameter
num_engines 0x01C RO Indicates value of number of engines parameter
max_input_width 0x020 RO Indicates value of maximum input video width parameter
max_output_width 0x024 RO Indicates value of maximum output video width parameter
Reserved 0x028-0x16C RO
int_control 0x170 RW Enables the interrupt
int_status 0x174 RW1C Read interrupt status and clear interrupt
Table 67.   vid_pid Register
Bits Name Description
31:16 VID Vendor ID that returns a value of 0x6AF7
15:0 PID Warp product ID that returns a value of 0x016F
Table 68.   version_numberRegister
Bits Name Description
31:0 Version Number The version number of the Warp IP
Table 69.   pipRegister
Bits Name Description
31:0 Pixels in Parallel The pixel in parallel parameter. Returns a value of 1 or 2.
Table 70.   color_planesRegister
Bits Name Description
31:0 Number of Color Planes The number of color planes parameter. Returns a value of 3.
Table 71.   bpsRegister
Bits Name Description
31:0 Bits per Color Sample The bits per color sample parameter. Returns a value of 10.
Table 72.   num_enginesRegister
Bits Name Description
31:0 Number of Engines The number of enginesparameter. Returns a value of 1 or 2.
Table 73.   max_input_widthRegister
Bits Name Description
31:0 Maximum input video width The maximum input video width parameter. Returns a value of 2048 or 3840.
Table 74.   max_output_widthRegister
Bits Name Description
31:0 Maximum output video width The maximum output video width parameter. Returns a value of 2048 or 3840.
Table 75.   int_controlRegister
Bits Name Description
0 Interrupt Enable Setting this bit to 1 will enable the interrupt. Setting to 0 will disable the interrupt.
Table 76.   int_status Register
Bits Name Description
0 Interrupt Status

Reading from this bit returns the status of the interrupt.

Writing a 1 to this bit will clear the interrupt. Once triggered, the interrupt will remain set until it is cleared by writing a 1 to this bit.

Level Two Title