Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

Protocol Converter Intel® FPGA IP Registers

Read and write access to the register map is via the Avalon memory-mapped compliant av_mm_control_agent interface. Turn on Enable memory mapped control interface, for access to this interface and access to the register map.

The av_mm_control_agent interface uses word addressing to access each register. The value the IP applies to the av_mm_control_agent_addresssignal should be the word address of the register to read or write to. Intel shows byte address of each register because Avalon memory-mapped host interfaces typically use byte addressing. Platform Designer applies any byte address to word address conversion if required

Table 8.  Protocol Converter Registers.
Register name Byte Address Access Description
Product ID 0x0 RO
Version number 0x4 RO
Conversion mode 0x8 RO A read to this register returns a value that specifies the input and output protocols for this instance of the Protocol Converter IP. A return value of 0 indicates that it converts from Avalon Streaming Video to Intel FPGA Streaming Video. A return value of 1 indicates that it converts from Intel FPGA Streaming Video to Avalon Streaming Video.
Enable debug 0xC RO A read to this register returns the value you select for the Enable debug parameter in this instance of the Protocol converter. The host software can read this value to determine which registers you can read
Reserved 0x10 – 0x11C RO Reserved for future use
Field width 0x120 WO If you select Intel FPGA Streaming Video Lite for Input protocol, this value specifies the frame width (in pixels) that the IP uses to create the output Avalon Streaming Video control packet. For 4:2:0 chroma sampling, this width represents the total number of luma samples per line, and you do not need to divide the image width in half.
Field height 0x124 WO If you select Intel FPGA Streaming Video Lite for Input protocol, this value specifies the frame height (in lines) that the IP uses to create the output Avalon Streaming Video control packet
Field interlace 0x128 WO If you select Intel FPGA Streaming Video Lite for Input protocol, this value specifies the frame interlace nibble that the IP uses to create the output Avalon Streaming Video control packet. Specify the value according to the 4-bit interlace nibble codes in the Avalon Streaming Video protocol. If 4-bit code specifies an interlaced , you should specify the interlace code that the IP should use for the first output frame. The f0/f1 indicator bit toggles automatically for subsequent frames.
Reserved 0x12C RO Reserved for future use
Color space 0x130 WO The value you write to this register specifies the color space of the incoming video. Write 0 for RGB, 1 for YCbCr and 2 for monochrome
Chroma sampling 0x134 WO The value you write to this register specifies the chroma sampling of the incoming video. 0 for 420, 2 for 422, and 3 for 444.
Reserved 0x138 RO Reserved for future use
Reserved 0x13C RO Reserved for future use
Status 0x140 RO The value you read from this register indicates the processing status of the IP.
Reserved 0x144 RO Reserved for future use
VIP control width 0x148 RO If you select Avalon Streaming Video, for Input protocol variant, a read to this register returns the frame width specified in the most recently received control packet. The width reported is a literal decode of the information in the control packet. If the data the IP processes is 4:2:0 chroma sampled, the width reported is half the actual frame or frame width.
VIP control height 0x14C RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the frame height specified in the most recently received control packet.
VIP control interlaced 0x150 RO If you select Avalon Streaming Video for Input protocol variant, a read to this register returns the interlace nibble specified in the most recently received control packet.
Control 0x154 WO Writes to this register instruct the IP to start processing video frames, or to stop processing at the next frame boundary. Write a 1 to bit[0] of this register to start the IP. Write a 0 to bit[0] to stop at the next frame boundary. If the IP is already at a frame boundary or is between frames when the write to stop occurs, it stops immediately and does not begin the next frame. The value of this register resets to 0, so if the av_mm_control_agent interface is turned on, the IP resets into the stopped state and you must write a 1 to bit[0] to begin processing
Reserved 0x158 WO Reserved for future use
Reserved 0x15C WO Reserved for future use
Table 9.  Status register
Bit Description
0

This bit indicates the IP is currently processing a frame. A value of 1 indicates that the IP is busy processing, a value of 0 indicates that it is idle.

When converting from Avalon Streaming Video to Intel FPGA Streaming Video, bit 0 is set to 1 at the start of the first packet belonging to each video frame. This packet can be a user packet, a control packet, or the frame packet. Bit 0 is then set back to 0 when the final cycle of data in the video frame packet is received.

When converting from Intel FPGA Streaming Video to Avalon Streaming Video the interpretation of bit 0 depends on if you turn on. If you turn on Enable low latency mode, the IP sets bit 0 to 1 when it receives the first pixel of the frame is received and sets to 0 when it receives the number of lines specified in register map address 73 (0x124). The IP holds bit 0 at 0 while it flushes any additional lines. If you do not turn on Enable low latency mode, the IP sets bit 0 to 1 at the start of the first frame received and it remains high until you reset the IP.

1 This bit indicates if the IP has fully processed at least one frame since the last reset. A 1 indicates that the IP has processed at least one, a 0 indicates that the IP has processed no frames.
2 This bit indicates if the last frame the IP receives has the expected number of pixels. A 0 indicates that the frame matched the width and height specified in the Avalon Streaming Video control packet or register map settings. A 1 indicates that the frame had too many or too few pixels according to these settings.
31:3 Unused.
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