Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 9/30/2021
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Document Table of Contents
Document Table of Contents x
About the Video and Vision Processing Suite Getting Started with the Video and Vision Processing IPs Video and Vision Processing IP Interfaces Video and Vision Processing IP Registers Protocol Converter Intel® FPGA IP 3D LUT Intel® FPGA IP Tone Mapping Operator Intel® FPGA IP Warp Intel® FPGA IP Document Revision History for Video and Vision Processing Suite User Guide
About the Video and Vision Processing Suite x
Device Family Support
Getting Started with the Video and Vision Processing IPs x
Video and Vision Processing IP Time-out Behavior Generating a Video and Vision Processing IP Simulating the Video and Vision Processing IPs
Protocol Converter Intel® FPGA IP x
About the Protocol Converter Protocol Converter Intel® FPGA IP Parameters Protocol Converter Intel® FPGA IP Functional Description Protocol Converter Intel® FPGA IP Interfaces Protocol Converter Intel® FPGA IP Registers
About the Protocol Converter x
Protocol Converter Release Information
3D LUT Intel® FPGA IP x
About the 3D LUT Intel® FPGA IP 3D LUT IP Parameters 3D LUT IP Block Description 3D LUT IP Registers 3D LUT IP Software API
About the 3D LUT Intel® FPGA IP x
3D LUT IP Features 3D LUT IP Release Information 3D LUT IP Performance IP and Resource Information
3D LUT IP Block Description x
3D LUT IP Interfaces Clocks Resets 3D LUT IP Latency
Tone Mapping Operator Intel® FPGA IP x
About the Tone Mapping Operator IP TMO IP Parameters TMO IP Block Description TMO IP Registers TMO IP Software API
About the Tone Mapping Operator IP x
TMO IP Features TMO IP Release Information TMO IP Performance and Resource Utilization
TMO IP Block Description x
TMO IP Interfaces TMO IP Latency
Warp Intel® FPGA IP x
About the Warp IP Warp IP Parameters Warp IP Block Description Warp IP Registers Warp IP Software API
About the Warp IP x
Warp IP Features Warp IP Release Information Warp IP Performance and Resource Utilization
Warp IP Block Description x
Warp IP Interfaces Warp IP Latency External Memory for Warp IP
Warp IP Software API x
Using Warp IP Software Warp IP Software Code Examples
About the Video and Vision Processing Suite
Getting Started with the Video and Vision Processing IPs
Video and Vision Processing IP Interfaces
Video and Vision Processing IP Registers
Protocol Converter Intel® FPGA IP
3D LUT Intel® FPGA IP
Tone Mapping Operator Intel® FPGA IP
Warp Intel® FPGA IP
Document Revision History for Video and Vision Processing Suite User Guide

3D LUT IP Interfaces

The IP has three functional interfaces.
The interfaces are:
  • Intel FPGA video stream input interface
  • Intel FPGA video stream output interface
  • Avalon Memory-Mapped compatible CPU interface

The 3D LUT IP control interface uses Avalon Memory-Mapped protocol to access control and RAM interface registers.

Clocks

The 3D LUT IP has two clock domains, each with a corresponding reset signal.

Table 13.  Clock domains
Clock name Description
cpu_clock CPU interface clock domain
vid_clock Video processing clock domain

The CPU interface uses little bandwidth and therefore does not impose a minimum clock frequency. The video clock frequency depends on the video resolution, frame rate, and the 3D LUT IP’s number of pixels in parallel. For example, a 300 MHz clock at 2 pixels in parallel supports active video resolutions up to 4096x2160 at 60 Hz.

All RTL-based blocks that transfer or receive data from a different clock domain include clock domain crossing (CDC) circuits for both, single bit and data bus signal cases. The CDC safely allow exchange of data between the two asynchronous clock domains. This principle applies to the control signals from the CPU interface to the main video datapath. The 3D LUT IP includes an .sdc file to constrain this CDC.

Resets

Table 14.  Resets associated to clock domainsBoth resets are synchronous active-high
Reset name Description
cpu_reset CPU interface clock domain reset.
vid_reset Video processing clock domain reset.
Related Information
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