Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2021

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Video and Vision Processing IP Registers

The IPs have compatible register maps. The register maps contain parameterization information.

In general, video and vision processing IP register maps have two distinctives areas:

  • A common area, which contains parameterization information. You can read to and write from components to determine the configuration, which allows portability of software and binaries between different video and vision processing platforms.
  • An IP-specific video and vision processing IP area, which contains functional configuration information for the specific IP.

Control interfaces use the Avalon memory-mapped interfaces. AXI4-Stream protocols are natively supported in Platform Design and can be automatically adapted to and from Avalon memory-mapped interfaces. Memory interfaces also use Avalon memory-mapped interfaces. You may also adapt them to AXI4-Lite as required in Platform Designer.

Table 4.  Register Map for Video and Vision Processing IPs
Register Word Address Access
Version number 0x1 RO
Unused 0x2 RO
IP parameterization registers 0x3:0x3F RO
Unused 0x40:0x51 RO
IP control registers 0x52:0xFFFF RW